Digital apparatus

ABSTRACT

Digital apparatus adapted to produce an output pulse having a time duration controlled by a digital word is disclosed. Such apparatus includes an addressable memory for storing a control bit in an address defined by the digital word and means actuated after the storage of the control bit for reading the contents of contiguous addresses of the memory and for initiating the output pulse and means for terminating such output pulse in response to the reading of the control bit from the memory.

United States Patent 1 McLeod, Jr. et al.

[ 1 Dec. 30, 1975 [541 DIGITAL APPARATUS [75] Inventors: Willard W.McLeod, Jr., Lexington;

John F. Heaton, Acton, both of Mass.

[73] Assignee: Raytheon Company, Lexington,

Mass.

[22] Filed: Apr. 25, 1974 211 App]. No; 464,076

[52] US. Cl. 340/173 R; 340/1725 [51] Int. CL G1 lC 13/00 [58] Field ofSearch 340/173 R, 172.5, 173 RC [56] References Cited UNITED STATESPATENTS 2,913,706 11/1959 Thorensen 340/1725 55W 5125mm com-man2,989.731 6/1961 Albanes 340/1715 Primary Examiner-Terrell W. FearsAttorney, Agent, or Firm-Richard M. Sharkansky;

Philip .1 McFarland; Joseph D. Pannone [5 7] ABSTRACT Digital apparatusadapted to produce an output pulse having a time duration controlled bya digital word is disclosed. Such apparatus includes an addressablememory for storing a control bit in an address defined by the digitalword and means actuated after the stor age of the control bit forreading the contents of contiguous addresses of the memory and forinitiating the output pulse and means for terminating such output pulsein response to the reading of the control bit from the memory.

6 Claims, 3 Drawing Figures COUNTER llllllllllllllllllll 1 n 5 ma b 0 Nmv g Q m no 5 El US. Patent Dec. 30, 1975 Sheet 2 of2 3,930,238

"5.5 5200 ozimmkw wm V N wE DIGITAL APPARATUS BACKGROUND OF THEINVENTION This invention relates generally to digital apparatus adaptedto produce an output pulse having a time duration controlled by adigital word applied to such apparatus and more particularly to digitalapparatus of such type which is used to control flux driven" phaseshifters in phased array antennas.

As is known in the art, phased array antennas may include many thousandsof antenna elements, each one including a phase shifter, toelectronically steer a beam from such an antenna to a desired directionin response to predetermined electrical signals out ofa beam steeringcomputer. Various types of phase shifters for such antennas aredescribed in detail in chapter l2, Phase Shifters for Arrays, of thebook entitled Radar Hand book," EditorJn-Chief Merrill I. Skolnik,published by McGraw-Hill Book Company, New York, New York, I970. Asdescribed on pages 12-43 through l245 of such book, when an analog phaseshifter (sometimes referred to herein as a flux driven phase shifter) isused in the phased array antenna, ferrimagnetic material of each phaseshifter is first driven to a reference point on the hysteresis loopassociated with such material, and then, in response to a control signalsupplied by the beam steering computer, such material is driven to adesired flux level on such hysteresis loop. The flux drive techniquegenerally uses the principle that the flux change in the ferrimagneticmaterial in each phase shifter is proportional to the time integral of avoltage applied to the phase shifter. Therefore, if the amplitude of thevoltage applied to the ferrimagnetic material in each phase shifter is aconstant, the resulting driven flux is proportional to the time durationof such voltage.

In one known technique used to provide a voltage pulse having a timeduration in accordance with a digital word applied by the beam steeringcomputer, the beam steering computer sequentially computes the digitalword for each of the phase shifters in an antenna array. As each suchdigital word is computed, such word is used to initialize the count" ofa digital counter. The computer also provides a set signal to aflip-flop, thereby raising the voltage level at the output of suchflip-flop at the time the counter is initialized. Clock pulses arecoupled to the counter and when the counter is full a reset" signal isapplied to the flipflop thereby to lower the voltage level at the outputof the flip-flop. The time duration of the voltage pulse developed atthe output of the flip-flop then is related to the number of clockpulses applied to the counter that are required to increase the count"of the counter from the initialized count" to the full count."

While such technique may be found adequate in many applications, suchtechnique generally requires a separate digital counter for each one ofthe phase shifters thereby adding to the weight, cost and complexity ofthe phased array antenna.

SUMMARY OF THE INVENTION In accordance with this invention digitalapparatus for producing a control pulse having a time duration inaccordance with a digital word includes: An address able memory meansfor storing a control bit in an address defined by the digital word;means, actuated after the storage of such control bit, for readingsequentially 2 the contiguous addresses of the memory means and forinitiating the control pulse; and, means for terminating such controlpulse in response to the occurrence of reading the control bit from thememory means.

In a preferred embodiment the memory means includes a plurality ofstorage cells arranged in a matrix of rows and columns. The digital wordout of the beam steering computer addresses a particular row of mem orycells. The first control bit is written into the mem ory cell located atthe addressed row and the first column. Succeeding digital wordssimilarly address rows of the memory means, and control bitscorrespondingly are written into a memory cell located at each addressed row and each successive column. After a control bit has beenwritten into the memory cell at the last column of the memory means,each row of storage cells is read sequentially and, concurrently withthe reading of the first row of cells, a control pulse is initiated.Such control pulse then causes a flux drive signal to be initiated foreach associated phase shifter, each such drive signal being terminatedwhen the control hit stored in the column associated therewith is readfrom the memory means. The pulse time duration to any associated phaseshifter then is equal to the time interval between the time the firstrow of cells is read and the time at which the control bit is read.

With such an arrangement a plurality of conventional random accessmemories and a single digital counter may be used to flux drive aplurality of phase shifters in a phased array antenna.

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding ofthe invention, reference is now made to the following description of apreferred embodiment and to the drawings, in which:

FIG. I is a simplified sketch of a radar system using an array ofantenna elements to radiate a collimated beam of radio frequency energyand to receive echo signals from targets illuminated by such radiatedenergy in accordance with this invention;

FIG. 2 is a block diagram of digital apparatus used in the radar systemof FIG. 1 according to the invention; and

FIG. 3 is a block diagram ofa random access memory used in the digitalapparatus of FIG. 2 according to the prior art.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, it maybe seen that a phased array antenna 10 includes a number of antennaelements 11, each here including a conventional "flux driven" phaseshifter (not shown) using a suitable ferrimagnetic material. The antennaelements 11 may be mounted in any conventional manner (not shown indetail) to form a space-fed planar array. Such an arrangement permitsradio frequency energy from a feed horn 17 to he collimated and directedin a beam as desired and echo signals returning to the individualantenna elements 11 to be focused on such feed horn 17, all inaccordance with digital control signals from a beam steering computerI5. Here such digital control signals, sometimes hereinafter referred toas digital words, are converted to voltage pulses of time dura tions inaccordance with such digital words by digital apparatus 19, the detailsof which will be discussed hereinafter. Suffice it to say here, however,that beam steering computer 15 produces, sequentially, digital words foreach of the phase shifters in the phased array antenna l0. Such wordsproduce control signals which, in turn, are converted into voltagepulses of different time durationsv Here such voltage pulses are appliedconcurrently to the phase shifters, thereby appropriately changing theflux drive to such phase shifters to direct the beam to the desireddirection.

Completing FIG. I, feed horn 17 is connected, in any convenient manner,as by waveguide (not numbered) to a transmitter/receiver 21. Theoperation of the transmitter/receiver 21 and the beam steering computeris controlled by a conventional synchronizer 23.

Referring now to FIG. 2, digital apparatus 19 is shown to include aplurality of, heren, identical read/- write random access memories 25,-Here such read/write random access memories 25,25,, are con' ventionalT-T-L (Transistor-TransistonLogic) semiconductor memories, each having64 memory cells arranged in a matrix of 4 columns and 16 rows asdescribed on page 9-232 of the book The Integrated Circuits Catalog forDesign Engineers," First Edition, published by Texas Instruments,Incorporated, (an exemplary one thereof, here random access memory 25,,being shown, for convenience, in FIG. 3). As shown in FIG. 3, randomaccess memory 25 includes: Four address terminals A, B, C, D; a writeenable terminal, WE,; four data input terminals D,, D D D and, four dataoutput terminals 8,, 8,, S 8,. In operation, when the level of thesignal on the write enable terminal, WE,, is high, each bit of the dataword applied to data input terminals D,D becomes stored in a row ofstorage cells, SC, such storage cells being disposed in columns C,C,,respectively, and in a row selected by the 4 bit digital word on addressterminals A, B, C, D. Such row selection is accomplished in aconventional manner because the 4 bit digital word applied to addressterminals A, B, C, D passes through a 4 to 16 decoder 27 (here made up,in a conventional way, of inverters and AND gates, not numbered,) toraise the level of one of the 16 output lines of such decoder inaccordance with the 4 bits of such 4 bit digital word to thereby addressthe storage cells disposed in one of the l6 rows. Thus, when the writeenable terminal, WE,, is high" the random access memory 25, is placed ina write" condition and each one of the 4 bits of the data word appliedto data input terminals D,D becomes stored in the storage cells disposedin a different one of the columns C,-C When the write enable terminal,WE,, is low" the random access memory 25, is placed in a read conditionand the storage cells disposed in a row addressed by the 4 bit digitalword applied to address terminals A, B, C, D are read and the datastored in the storage cells disposed in columns C,-C of such selectedrow appear on output lines S,-S respectively. That is, output lines S,S,are, in effect, associated with columns C,C,, respectively, during the"read" condition.

Referring new again to FIG. 2, the random access memories 25,-25, havefour address terminals A, B, C, D coupled to beam steering computer 15and to a 4 bit counter through read/write address selectors 29,29,,,respectively, as shown. An exemplary one of the read/write selectors29,-29,,, here read/write selector 29,, is shown to include: (a) A firstset of AND gates 32,42 such AND gates being enabled, when random accessmemory 25, is in a write" condition, to pass the digital word suppliedby beam steering computer 15 (via OR gates 34,-34,,) to such randomaccess memory; and, (b) a second set of AND gates 36,36 such second setof AND gates being enabled, when the random access memory 25, is in aread" condition (because of inverter 35), to pass the digital wordsupplied by counter 30 (via OR gates 34,34,) to such random accessmemory. It follows then that when the random access memory 25, is in awrite condition (i.e. when the signal on terminal WE, is high") thedigital word produced at the output of the beam steering computer 15provides the write address for such random access memory and when suchrandom access memory is in a read" condition (i.e. when the signal onterminal WE, is low") the digital word stored in counter 30 and producedat the output of such counter provides the read address for such randomaccess memory.

Each one of the random access memories 25,-25,, has its output terminalsS,S coupled to a different set of four phase shifters in the antennaarray through pulse forming networks 40,-40,, as shown. An exemplary oneof such pulse forming networks 40,-40,, here pulse forming network 40,is shown to include four flip-flops 42,-42 (each of conventional design)the set terminal (S) of each thereof being coupled to a read line 60 andthe reset terminal (R) of each one thereof being coupled to a differentone of the output terminals 5 -8 as shown. The output of each one of theflipflops 42,--42, is coupled to a different one of a set of phaseshifters PS,-PS as shown.

Random access memories 25,-25,, have data input terminals D,-D, coupledto a controller 44 and a comparator network 46 through logic networks48,-48,,, respectively, as shown.

Comparator network 46 includes three serially coupled, four stageregisters, REG,-REG the first one thereof being coupled to the output ofbeam steering computer 15, as shown. Each one of such registersREG,-REG,, stores the 4 bit binary word applied to its input in responseto the trailing edge of each one of the clock pulses applied to linec.p. Comparators COMP- ,-COMP: have one input coupled to the output ofbeam steering computer 15 and another input coupled to the output ofregisters REG,-REG,,, respectively, as shown. Comparators COME-COMP, arehere of any conventional design and are adapted to produce a "high" orbinary 1 signal at their output when the data applied to their inputsare equal and to produce a low or binary 0 signal when such inputs arenot equal. The output of comparator COMP,, (i.e. output W,) is fed tothree AND gates 51,, 51,, 51 as indicated. Likewise, the output ofcomparator COMP, (i.e. output W,) is fed to two AND gates 51,, 51,, asindicated, and the output of comparator COMP, (i.e. output W is fed toAND gate 51 An exemplary one of the logic networks 48,-48,,, here logicnetwork 48,, is shown to include three OR gates 50,-50 OR gate 50,couples data input terminal D of RAM 25, to the output of AND gates 51,,51 and 51,, of comparator network 46 and to data output terminal D, ofcontroller 44; OR gate 50 couples data input terminal D of RAM 25, tothe output of gates 51, and 51 of comparator network 46 and to dataoutput terminal D of controller 44; and, OR gate 50,-, couples datainput terminal D of RAM 25, to the output of gate 51,, of comparatornetwork 46 and data output terminal D of controller 44. Data inputterminal D of RAM 25, is directly coupled to data output terminal D, ofcontroller 44, as indicated.

Controller 44 includes two shift registers 52, 54. Shift register 52 ishere a four stage recirculating shift register of any conventionaldesign, stages 52,-52 being coupled to output terminals D,'D,',respectively, as shown. Output terminals D D and D (in addition to beingconnected to the logic networks 48, 48,, as just described) are alsoconnected to the comparator network 46. Thus, the output terminal D iscoupled to AND gate 51, of comparator network 46, output terminal D iscoupled to AND gates 51 and 51,, of such network and output terminal Dis coupled to AND gates 51 51 51 of such network, as shown. Shiftregister 54 here has n stages 54,54,,, such stages being coupled toterminals WE,WE,,, respectively, as shown. Shift register 52 is coupledto beam steering computer through clock pulse line c.p. and shiftregister 54 is coupled to data output line D, of shift register 52 andclock pulse line c.p. through AND gate 56. Shift registers 52, 54 arehere constructed to shift a binary one from stage to stage in responseto the trailing edge of each clock pulse applied to line c.p., allstages other than the stage containing a binary one containing a binaryzero.

In operation, shift registers 52 and 54 are initialized, (by anyconvenient means, not shown,) so that a binary l is stored in stages 52,and 54,, and a binary 0 is stored in each one of the other stages ofsuch shift registers (i.e. stages 52 -52 and 54 -54 Such initializedcondition is indicated in FIG. 2. (It is here noted that a binary 1 ishere defined as a high" level signal, and a binary 0 as a low" levelsignal.)

After such initialization, beam steering computer 15 produces at itsoutput a sequence of digital words and, concurrently with each one ofsuch produced digital words, a clock pulse on line c.p. Here such clockpulses and digital words are produced at regular time intervals. (Aswill become apparent hereinafter, each one of such digital wordsrepresents the time interval between the time a selected one of the flipflops 42,-42 of pulse forming networks 40,-40, is set" and the time suchselected flipflop is reset." It follows then that each one of suchdigital words designates the desired time duration of a voltage pulseproduced at the output of the selected flip-flop and applied to aselected one of the phase shifters PS,-PS Continuing then, because abinary 1 is initially stored in stages 52, and 54,, only the randomaccess memory 25, is placed in a write condition and the data applied tothe data input terminals (D,D,) thereof is binary I000. Therefore, whenthe first digital word is produced at the output of beam steeringcomputer 15, such digital word passes through read/write addressselector 29, to random access memcry 25, and thereby provides a writeaddress for such random access memory. Also, the data applied to inputterminals D,-D,,(i.e. binary 1000) becomes stored in the row of storagecells selected by the digital word produced at the output of beamsteering computer 15 (i.e. the storage cell disposed in the firstcolumn, C,, of such selected row has a binary 1 stored therein and thememory cells disposed in columns C -C of such se lected row having abinary 0 stored therein).

In response to the trailing edge of the first clock pulse: (a) the firstdigital word produced by beam steering computer also becomes stored inregister REG,; and (b) the binary l in register 52 is shifted from stage52, to stage 52 (that is, the data at data output terminals D,'-Dbecomes binary 0l00). It follows then that, if the first and seconddigital words out of the beam steering computer 15 are not equal, whenthe second digital word is produced at the output of the beam steeringcomputer 15, the data word binary 0100 becomes stored in random accessmemory 25, in the storage cells disposed in the row selected by suchsecond digital word (the storage cell in the second column, C having abinary l stored therein). If the first digital word produced by the beamsteering computer is the same as the second digital word a binary l isproduced on line W,. Because data output terminal D is high, such binary1 passes through AND gate 51, and OR gate 50, to data input terminal Dand becomes restored" in the memory cell disposed in the column C, andin the row selected by the first digital word (because under thiscondition the first and second digital words are equal).

In response to the trailing edge of the second clock pulse: (a) thebinary l in stage 52 shifts to stage 52 and the data applied to dataoutput terminals D,'-D.,' is binary 0010; and (b) the first digital wordproduced by the beam steering computer 15 becomes stored in register REGand the second digital word becomes stored in register REG, It followsthen that, if the third digital word is not equal to the first or seconddigital word when the third digital word is produced at the output ofbeam steering computer 15, the data 0010 becomes stored in random accessmemory 25, at the storage cells disposed in the row selected by suchthird digital word; the storage cell in the third column, C having abinary l stored therein. If the third digital word is equal to the firstdigital word a binary l is produced on line W and, because the signal onoutput data terminal 0;, is high, such binary l passes through AND gate51 and OR gate 50, to data input terminal D, to become restored in thememory cell disposed in column C, and the row selected by the thirddigital word. Also, if the third digital word is equal to the seconddigital word a binary l is produced on line W,, and, because the signalon output data terminal D is "high," such binary 1 passes through ANDgate 51 and OR gate 50 to data input terminal D, to become restored inthe memory cell disposed in column C and the row selected by the thirddigital word.

In response to the trailing edge of the third clock pulse: (a) thebinary l in stage 52 shifts to stage 52 and the data applied to dataoutput terminals D,'D,' is binary 0001; and (b) the first digital wordbecomes stored in register REG the second digital word becomes stored inregister R50 and the third digital word becomes stored in REG,.Therefore, if the fourth digital word is not equal to the first, second,nor third digital words, when the fourth digital word is produced at theoutput of the beam steering computer 15, the data 0001 becomes stored inrandom access memory 25, at the storage cells disposed in the rowselected by such digital word; the storage cell disposed in the fourthcolumn, C having a binary l stored therein. If the fourth digital wordis equal to the first digital word a binary l is produced on line W;and, because the signal on output data terminal D is high, such binary 1passes through AND gate 51,, and OR gate 50, to data input terminal D,to become stored in the memory cell disposed in column C and the rowselected by the third digital word. If the fourth digital word is equalto the second digital word a binary l is produced on line W and, becausethe signal on output terminal D. is high," such binary 1 passes throughAND gate 51,, and OR gate 50 to data input terminal D to become storedin the memory cell disposed in column C and the row selected by thefourth digital word, If the fourth digital word is equal to the thirddigital word a binary l is produced on line W and passes to data inputterminal D to become stored in the memory cell disposed in column C andthe row selected by the fourth digital word. Further, the binary I nowstored in stage 52., serves as an enabling signal for AND gate 56 sothat in response to the trailing edge of fourth clock pulse the binary lin stage 54, shifts to stage 54 Additionally, in response to thetrailing edge of the fourth clock pulse the binary l stored in stage 52shifts to stage 52 and the data applied to data output terminals D,'D isbinary 1000 thus allowing the above described process to continue forrandom access memories 25 -25 successively.

It follows then that a binary l or control bit will be stored in randomaccess memory 25 at the storage cells in the rows addressed by thefifth, sixth, seventh and eighth digital words produced by the beamsteering computer a binary I being stored in the storage state in columnC and the row addressed by the fifth digital word, a binary I beingstored in the storage cell in column C and the row addressed by thesixth digital word, a binary I being stored in the storage cell incolumn C and the row addressed by the seventh digital word, and a binary1 being stored in the storage cell in column C and the row addressed bythe eighth digital word.

The process continues until a binary l is stored in the storage cell inrandom access memory n disposed at column C and the row addressed by the4nth digital word produced by beam steering computer 15. Here inresponse to the next (i.e. the 4n+l) clock pulse, shift register 54 hasa binary 0 stored in each one of the stages 54,54,,, the signals onterminals WE,WE,, become low" thereby: (I) enabling NOR gate 58 todevelop an enabling signal on line 60; (2) placing random accessmemories 25 -45, in a read condition, and (3) enabling the contents ofcounter to pass through read/write address selectors 29 -29,, to randomaccess memories 25 -25,, respectively so that such contents serves asread addresses for such memories.

Line 60 is coupled to AND gate 62 and to the set terminals (S) of theflip-flops 42 -42 of pulse forming networks -40,. The enabling signal online serves to: (1) allow clock pulses on clock pulse line c.p. to passthrough AND gate 62 to counter 30, such counter 30 having been initiallyset to binary 0000 by any convenient means (not shown); and (2) set allflip-flops 42,-42 in all networks 40,-40,,.

Therefore, at the commencement of the read operation: all the randomaccess memories 25,-25, are placed in a read" condition thereby couplingthe read address terminals A, B, C, D of random access memories 25,-25,to the output of the counter 30, such counter addressing the randomaccess members 25,-25, at location binary 0000; and all flip-flops inthe pulse forming networks 40 40,, are placed in a set condition so thata voltage pulse is commenced. such being coupled to each one of thephase shifters, PS,PS,,,. It follows then that since the first row R ofall the random access memories 25,-25 are being read addressedsimultaneously during the 4n+lst clock pulse, if a binary l is stored inthe storage cell in the first row of any one of such memory, theflip-flop cou pled to any such storage cell disposed in row R, will be 8reset thus terminating the voltage pulse coupled to the phase shifterfed by such flip-flop.

During the next clock pulse (i.e. 4n+2) the counter 30 counts up 1 c.p.and its contents change to 000l. Therefore, the second row (R of all therandom access memories 25 -25, are read simultaneously and if a binary lis stored in the storage cell in the second row (R of any one of suchmemories, the flip-flop coupled to such storage cell will be reset thusterminating the voltage pulse coupled to the phase shifter fed by suchflip-flop to produce a voltage pulse clock pulse in duration. Theprocess continues until the memory cells in all 16 rows of all therandom access memories have been read.

In summary then, each one of the digital words pro duced at the outputof the beam steering computer by providing a write address for aparticular row of storage cells in the random access memories 25 -25,,where a binary l, or control bit is to be stored, in effect representsthe time duration (i.e. the number of clock pulses, O clock pulses to 16clock pulses) between the commencement of the read" operation (and hencethe start of a voltage pulse) and the time at which such control bit isread. To put it another way, the voltage pulses produced at the outputof the flip-flop 42 -42 of pulse forming network 40 -40,, are commencedsimultaneously, i.e. when an enabling signal is developed on line 60.Each one of the flip-flops 42,-42 in each one of the pulse formingnetworks 40,40, is associated with the storage cells in a different oneof the columns C -C of each one of the random access memories 25 -25Because the memory cells in each row are read sequentially at each clockpulse, each one of such flip-flops is reset at the time the control bit(or binary l) stored in the column associated therewith is read, suchreset time being related to the row in such column where the storagecell containing such control bit is disposed. The reset flip-flopthereby terminates the voltage pulse produced at its output.

Threfore, after the 4n+l6th clock pulse all phase shifters are in theirproper flux driven condition thereby enabling the beam of radiation tobe directed in the desired direction.

Having described a preferred embodiment of this invention, it is evidentthat other embodiments incorporating its concepts may be used. Forexample, if random access memories 25,-25, were constructed so that,during the write" operation, each one of the rows of storage cells couldbe independently selected for writing data, the comparator network 46could be eliminated.

It is felt, therefore, that this invention should not be restricted toits disclosed embodiments but rather should be limited only by thespirit and scope of the appended claims.

What is claimed is:

1. Digital apparatus for producing a set of pulses having time durationsin accordance with corresponding digital words applied sequentially tosuch digital apparatus comprising:

a. addressable memory means having storage cells arranged in rows andcolumns;

b. means for applying a control bit to a different one of the columns ofstorage cells synchronously as each one of the digital words is appliedto the digital apparatus;

c. means for enabling storage of such control bit in the row addressedby such applied one of the digital words;

d. a plurality of pulse generating means, each one thereof being coupledto a common actuating line and having a terminating line connected to acorresponding one of the columns of storage cells, each one thereofinitiating one of the set of pulses in response to a signal beingapplied to the actuating line and for terminating such one of the pulsesin response to a signal being applied to the terminating line;

e.'means, actuated in response to the last one of a predetermined numberof applied digital words, for sequentially reading each one of the rowsof storage cells and for applying a signal to the actuating line toinitiate simultaneously each one of the set of pulses; and,

f. means for applying signals to a different one of the terminatinglines in response to the reading of a different one of the storedcontrol bits thereby to terminate a different one of such pulses attimes corresponding to the successively applied digital words.

2. The apparatus recited in claim 1 wherein each one of the pulsegenerating means is a flip-flop having a set terminal coupled to theactuating line and a reset terminal coupled to the terminating line.

3. Digital apparatus for producing a set of pulses having time durationsin accordance with corresponding digital words applied sequentially tosuch digital apparatus, comprising:

a. an addressable memory having storage cells arranged in a matrix ofrows and columns;

b. a plurality of pulse generating means, each one thereof being coupledto a common actuating line and having a terminating line connected to acorresponding one of the columns of storage cells, each one thereofinitiating one of the set of pulses in response to a signal beingapplied to the actuating line and for terminating such one of the pulsesin response to a signal applied to the terminating line thereof;

c. means for write addressing the storage cells in the columns thereofsequentially as the digital words are sequentially applied to thedigital apparatus and for writing a control bit into such ones of thestorage cells located at both the write addressed columns and rowsspecified by the applied digital words; and,

d. means, actuated in response to the last one of a predetermined numberof applied digital words, for sequentially reading each one of the rowsof storage cells including means for applying a signal to the actuatingline at commencement of such sequential reading to initiatesimultaneously each one of the set of pulses, and for applying signalsto the terminating lines in response to reading the stored control bits,thereby to terminate such pulses at times corresponding to the digitalwords.

4. The digital apparatus recited in claim 3, wherein each one of thepulse generator means is a flip-flop having a set terminal coupled tothe actuating line and a reset terminal coupled to the terminating line.

5. The digital apparatus recited in claim 1 wherein each one of thestorage cells comprises an electrical circuit.

6. The digital apparatus recited in claim 3 wherein each one of thestorage cells comprises an electrical circuit.

1. Digital apparatus for producing a set of pulses having time durationsin accordance with corresponding digital words applied sequentially tosuch digitAl apparatus comprising: a. addressable memory means havingstorage cells arranged in rows and columns; b. means for applying acontrol bit to a different one of the columns of storage cellssynchronously as each one of the digital words is applied to the digitalapparatus; c. means for enabling storage of such control bit in the rowaddressed by such applied one of the digital words; d. a plurality ofpulse generating means, each one thereof being coupled to a commonactuating line and having a terminating line connected to acorresponding one of the columns of storage cells, each one thereofinitiating one of the set of pulses in response to a signal beingapplied to the actuating line and for terminating such one of the pulsesin response to a signal being applied to the terminating line; e. means,actuated in response to the last one of a predetermined number ofapplied digital words, for sequentially reading each one of the rows ofstorage cells and for applying a signal to the actuating line toinitiate simultaneously each one of the set of pulses; and, f. means forapplying signals to a different one of the terminating lines in responseto the reading of a different one of the stored control bits thereby toterminate a different one of such pulses at times corresponding to thesuccessively applied digital words.
 2. The apparatus recited in claim 1wherein each one of the pulse generating means is a flip-flop having aset terminal coupled to the actuating line and a reset terminal coupledto the terminating line.
 3. Digital apparatus for producing a set ofpulses having time durations in accordance with corresponding digitalwords applied sequentially to such digital apparatus, comprising: a. anaddressable memory having storage cells arranged in a matrix of rows andcolumns; b. a plurality of pulse generating means, each one thereofbeing coupled to a common actuating line and having a terminating lineconnected to a corresponding one of the columns of storage cells, eachone thereof initiating one of the set of pulses in response to a signalbeing applied to the actuating line and for terminating such one of thepulses in response to a signal applied to the terminating line thereof;c. means for write addressing the storage cells in the columns thereofsequentially as the digital words are sequentially applied to thedigital apparatus and for writing a control bit into such ones of thestorage cells located at both the write addressed columns and rowsspecified by the applied digital words; and, d. means, actuated inresponse to the last one of a predetermined number of applied digitalwords, for sequentially reading each one of the rows of storage cellsincluding means for applying a signal to the actuating line atcommencement of such sequential reading to initiate simultaneously eachone of the set of pulses, and for applying signals to the terminatinglines in response to reading the stored control bits, thereby toterminate such pulses at times corresponding to the digital words. 4.The digital apparatus recited in claim 3, wherein each one of the pulsegenerator means is a flip-flop having a set terminal coupled to theactuating line and a reset terminal coupled to the terminating line. 5.The digital apparatus recited in claim 1 wherein each one of the storagecells comprises an electrical circuit.
 6. The digital apparatus recitedin claim 3 wherein each one of the storage cells comprises an electricalcircuit.